1. Field of the Invention
This invention relates to a memory construction apparatus, and more particularly to a memory construction apparatus for constructing logical memories in designing an integrated circuit.
2. Description of the Related Art
ASIC (Application Specific Integrated Art) is the generic name for custom ICs (Integrated Circuits) designed e.g. for specific purpose control, and differently from a general-purpose chip, it is a new dedicated chip designed in accordance with specifications desired by an equipment manufacture.
When an equipment manufacturer develops a product, they generally design the product using a general-purpose chip already available, but when an IC specialized for a specific function is desired, they employ a so-called custom ASIC.
Since the ASIC is specialized for a specific function, it is possible to manufacture a product that consumes less power than when a circuit is constructed using a general-purpose IC. Further, reduction of a mounting area and enhancement of operating speed can be expected.
When an ASIC having a memory function is developed, normally, memory macros, such as several kinds of physical RAMs (Random Access Memories) and FFs (Flip Flops), prepared in advance as libraries, are used (the term “macro” is intended to mean a circuit block having a specific function), and a circuit is described and generated according to a logically required memory space (logical memory space) using an HDL (Hardware Description Language: logical description language for designing an integrated circuit).
Conventionally, a technique for developing an ASIC has been proposed which uses a memory compiler and produces a memory (physical RAM) from memory specifications input to the memory compiler (see e.g. Japanese Laid-Open Patent Publication (Kokai) No. H9-171527 (Paragraph numbers [0006] to [0010], and FIG. 1).
However, there is an upper limit to the capacity of the memory which can be produced with the memory compiler by the conventional ASIC-developing technique, and therefore when the capacity of a logically required memory exceeds the upper limit, it is necessary to produce a circuit of a logical memory by combining several physical RAMs produced by the memory compiler and perform circuit debugging (using logic simulation), which causes an increase in TAT (Turn Around Time: a time period taken to perform a sequence of processes).
Further, it is difficult to predict how many physical RAMs are required at the beginning of design, and hence it is difficult to select from devices, such as an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), and a Structured ASIC, which are limited in the numbers of usable physical RAMs and usable FFs. Even if a device is selected based on a prediction of the number of physical RAMs to be used, a larger number of physical RAMs than predicted sometimes come to be used depending on the combination of RAMs. This can eventually cause the number of physical RAMs to exceed the limited number of usable RAMs, which compels a change in the combination of RAMs (change in the circuit), and further in the worst case, a change in the device.